The memory controller is only in control of making certain that memory & cache on diverse processors stays regular - when you create to memory on CPU1, CPU2 will not be capable to read through something else from its cache. It's not its duty to make certain that they're equally making an attempt to manipulate the same information. There are some low stage instructions used locking and atomic operations.
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Simple, common definition: for those who disassemble a high-level language instruction and it yields accurately one assembler instruction, it it atomic. If it yields much more than one assembler instruction, It's not at all atomic.
– jogojapan Commented Nov two, 2012 at 12:08 five @BoPersson Ah. That is proper. For your OP: Indeed this implementation permits concurrent use of the elements of your vector, although not the vector itself. If, say, one thread modifies the worth stored in on the list of atomics while A further thread provides new components to the vector, a vector reallocation may well take place and the object the 1st thread modifies could be copied from 1 position inside the vector to a different.
Should the "preset sizing at design" limitation is simply too onerous, You may use std::deque in its place. This allows you to emplace
Without a doubt, the variable is published applying two different functions: one which writes the primary 32 bits, and also a next one which writes the final 32 bits. Meaning that A further thread could possibly browse the worth of foo, and see the intermediate state.
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See also Can num++ be atomic for 'int num'? re: x86 atomic RMWs in general, a fewer concise rationalization of precisely the same point you wrote here.
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When two threads do the job at the same time on the shared variable and one of those steps consists of composing, the two threads must employ atomic functions.